Many high-speed, chip-to-chip electrical input/output interconnects are implemented as differential data links. In such a system, a data bit may be transmitted as signals on a positive signal path and a negative signal path. The data bit can be resolved at a receiver by subtracting the two signals and sampling the result. In such systems, the propagation of the signals along both paths must be maintained in synchrony to permit accurate data resolution with the signals. This typically requires careful matching of positive and negative path lengths. However, as data rates reach beyond multiple Gb/s (gigabits per second), intra-pair skew, e.g., time of flight differences between signals on one or more pairs of wires that constitute the differential link, may limit the achievable bit-error rate. Intra-pair skew may also be associated with mismatches in passive components and/or active devices, as well as wire parasitics. Intra-pair skew may result in received signals that are not fully differential because they may be somewhat affected by noise that would otherwise be cancelled during differential data resolution in the non-skewed case. Intra-pair skew may also reduce a receiver's timing margin.
Thus, there is a need for improved devices, systems and methods to address intra-pair skew.